Job Description:
Implementing and verifying DFT-centric modules such as at-speed scan, BIST, JTAG, etc. Overall DFT-related timing. Yield analysis, post silicon validation. Internal flow development such as low power support, functional test fault grading. Mentoring junior DFT engineers as needed.
Functional Area: IT Software – Embedded/EDA/VLSI/ASIC/Chip Design
Industry Type: Semiconductors/Electronics
| Experience | 5 - 7 Years | ||
|---|---|---|---|
| Role | Database Architect/Designer | ||
| Skills Required | BSEE required, MSEE preferred with 5+ years of experience in DFT. Strong hands-on experience in logic design/debug and simulation background. Static timing analysis and mixed-signal simulation experience a big plus. Must be fluent in ATPG, JTAG (AC, DC), fault simulation, etc. Good programming and scripting skills such as Perl, C++, Tcl, etc. | ||
| Education | UG - B.Sc - Electronics PG - M.Sc - Electronics | ||
| Contact | Visit http://www.rambus.com | ||
| Website | http://www.rambus.com | ||
| Company Profile | Rambus is one of the world’s premier technology licensing companies. Founded in 1990, the Company specializes in the invention and design of architectures focused on enriching the end-user experience of electronic systems. | ||
| Remuneration Per Annum | Not Specified | ||
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