Job Description:
As a senior integration design engineer 1, you will be responsible for full-chip integration of complex custom and mixed-signal hard-IPs in next generation FPGAs. You will lead full-chip timing closure using Static-timing analysis techniques. You will be an expert in Full-chip EM/IR, power and clock routing, custom layout integration, sign-off release checks including electrical and functional verification.
Industry Type: Semiconductors/Electronics
| Experience | 4 to 9 years. | ||
|---|---|---|---|
| Role | Design Engineer | ||
| Skills Required | Qualifications include a MSEE or equivalent with minimum 5 years direct related experience in IC Design and have several successful product tape-outs. Other qualifications include: IC design experience at the IP block level. Cadence SKILL coding is a plus. Expert in shell/PERL/TCL/Python and other scripting tools. Team-work across global teams. Effective communication skills. | ||
| Education | (UG - B.Tech/B.E. - Electrical, Electronics/Telecomunication) OR (PG - M.Tech - Electrical, Electronics/Telecomunication) | ||
| Contact | ravikir@xilinx.com | ||
| Website | http://www.xilinx.com/ | ||
| Company Profile | Since our founding more than 25 years ago, Xilinx has been a semiconductor industry leader at the forefront of technology, market and business achievement. | ||
| Remuneration Per Annum | Not Specified | ||
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